Magnetoresistive Random Access Memory (MRAM) is an emerging technology that may be competitive with prior integrated circuit memory technologies, such as floating gate technology. The MRAM technology may integrate silicon-based electronic components with magnetic tunnel junction technology. A significant element in MRAM is the magnetic tunnel junction (MTJ) where information may be stored. A MTJ stack has at least two magnetic layers separated by a non-magnetic barrier, where a fixed layer has a set magnetic property and a free layer has a programmable magnetic property for storing information. If the fixed layer and the free layer have parallel magnetic poles, the resistance through the MTJ stack is measurably less than if the fixed layer and the free layer have anti-parallel poles, so parallel magnetic poles may be read as a “0” and anti-parallel poles may be read as a “1.” The MTJ stack is typically incorporated into a memory cell, and many memory cells with MTJ stacks are incorporated into a memory bank.
Contacts are formed underlying the MTJ stack, where the contacts are utilized to integrate the MTJ stack into the integrated circuit. The contacts pass through interlayer dielectrics, and are typically formed by etching a via through the interlayer dielectric and then filling the via with an electrically conductive material. When the top surface area of the base contact is larger than a memory cell bottom surface area that overlies the base contact, the overlap of conductive material from the base contact can produce shorts that impair the function of the memory cell. However, forming a narrow via for the base contact produces a high aspect ratio of the via depth to the via width. This high aspect ratio often results in voids or gaps within the conductive material of the contact that is formed within the via. The voids in the contact undesirably reduce the strength and conductivity of the contact.
Accordingly, it is desirable to provide integrated circuits with memory cells and underlying base contacts, where a base contact top surface area is less than a memory cell bottom surface area, and methods of producing the same. In addition, it is desirable to provide integrated circuits with fewer shorts than comparable integrated circuits with wider base contacts, and methods of producing the same. Furthermore, other desirable features and characteristics of the present embodiments will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.